Modulation Plugin

This project aims to develop an Modulation Plugin Module, to be used in conjunction with a 8/16 bits embedded system such as the dsPic33F development board.

ToDo

• Voltage during "Lo" time of DAC can also be set (i.e. not necessary zero)
• modulation cct & PCb
  • Bias resistors for op-amp
  • crystal & SMD res. too close, easy to short when soldering
  • footprint of some chips are too small, enlarge it for easily soldering
  • some cct modification
    • modify the res. value

Objectives

• The modulation module is used to deliver a digital output signal with the following characteristics:
  • Square wave
  • Variable frequency (0 - >10kHz)
  • Variable amplitude (0V - 2.5V)
  • Accuracy frequency response (error < 2%)
• interface to MCU which do the control

Software Solution

• Timer Interrupt controlling I2C DAC can only achieve frequency response of about 500Hz
  • 5byte/cmd
  • 8bit/byte
  • baudrate = 400kHz
  • This yields 10kHz (0.1ms)
  • As OS context switch is 10ms, set timer to 1ms (1kHz), so that 0.9ms can be used to process other tasks
  • timer frequency of 1kHz yields a modulation frequency of 500Hz
• Due to higher freq. response requirement, so using hardware to implement the clock

Hardware Solution

Overall Performance

• I2C Baudrate: 400kHz
• Output Voltage Range: 0 - 3.3V
• Output Frequency Range: 0 - 200kHz
  • Cannot reach higher frequency due to minimum time to execute code in interrupt routine is about 500ns
• Number of channels: 4
• Accuracy of frequency: <2%
  • Conditions: external crystal, no OS context switch, single channel operation
  • Measurements (by scope)
    • +/-2.100kHz@200kHz => 1.05%
    • +/-0.520kHz@100kHz => 0.52%
    • +/-0.140kHz@50kHz => 0.28%
    • +/-0.006kHz@10kHz => 0.06%
    • +/-0.002kHz@5kHz => 0.04%
    • +/-0.200Hz@1000Hz => 0.02%
    • +/-0.000Hz@500Hz => 0.00%
    • +/-0.000Hz@100Hz => 0.00%
    • +/-0.0001Hz@50Hz => 0.02%
    • +/-0.000Hz@10Hz => 0.00%
    • +/-0.000Hz@5Hz => 0.00%
• Accuracy of frequency: <2%
  • Conditions: external crystal, no OS context switch, 4 channel operation, Ch2 = 1kHz, Ch3 = 50kHz, Ch4 = 200kHz
  • Measurements of ch1 (by scope)
    • +/-2.000kHz@200kHz => 1.00%
    • +/-0.520kHz@100kHz => 0.52%
    • +/-0.130kHz@50kHz => 0.26%
    • +/-0.130kHz@10kHz => 0.06%
    • +/-0.002kHz@5kHz => 0.04%
    • +/-0.200Hz@1000Hz => 0.02%
    • +/-0.100Hz@500Hz => 0.02%
    • +/-0.000Hz@100Hz => 0.00%
    • +/-0.010Hz@50Hz => 0.01%
    • +/-0.000Hz@10Hz => 0.00%
    • +/-0.001Hz@5Hz => 0.02%

Selected Chips

Part No.	Description
DAC7574IDGS	Quad-channel 12-bit I2C DAC
dsPIC33FJ256GP506-I/PT	uP programed as I2C Quad-channel programmable clock[*]
SN74AHC4066PWR	Quad-channel Bilateral Analog Switch
OPA4340EA	Single-Supply, Quad-channel, Rail-to-Rail Operational Amplifiers

• [*]Alternatives: DS1089L: 3.3V Center Spread-Spectrum EconOscillator

Circuit

                    +-----+            +--------+         +--------+
      I2C Bus       |     |            | Analog |         | Op-Amp |
  ------------+-----| DAC |------------| Switch |---------|        |---------Output
              |     |     |            +--------+         +--------+
              |     +-----+                |
              |                            |
              |     +--------------+       |
              |     | Programmable |       |
              +-----| Clock        |-------+
                    +--------------+
  

• This architecture allows the square wave to run at a very high frequency, even with a slow I2C and a slow DAC.

Circuit Simulation by Paul Falstad's Web

• Import the following

$ 1 5.0E-6 16.817414165184545 64 5.0 50
w 128 256 144 256 0
w 16 256 64 256 0
g 16 352 16 368 0
v 64 64 112 64 0 0 40.0 2.5 0.0 0.0 0.5
w 112 128 144 128 0
w 64 128 16 128 0
w 16 128 16 256 0
v 64 256 128 256 0 2 1000.0 1.65 1.65 0.0 0.5
a 336 144 464 144 1 3.3 0.0
w 336 160 336 192 0
w 464 192 464 144 0
w 464 144 512 144 0
r 592 144 592 256 0 1000.0
g 592 352 592 368 0
w 512 144 592 144 0
w 336 192 352 192 0
w 432 192 464 192 0
v 64 128 112 128 0 1 1.0 1.25 1.25 0.0 0.5
w 16 256 16 288 0
w 16 288 16 352 0
w 592 256 592 352 0
g 272 352 272 368 0
w 272 128 336 128 0
w 176 256 176 144 0
r 272 224 272 288 0 10000.0
w 272 128 272 224 0
w 272 288 272 352 0
159 144 128 208 128 0
r 208 128 256 128 0 10000.0
w 256 128 272 128 0
w 144 256 176 256 0
r 336 224 336 288 0 10000.0
g 336 352 336 368 0
w 336 288 336 352 0
w 336 192 336 224 0
r 352 192 432 192 0 10000.0
o 4 64 0 34 2.5 9.765625E-5 0 -1
o 0 64 0 35 5.0 9.765625E-5 1 -1
o 11 64 0 34 2.5 3.90625E-4 2 -1

SVN Server

• Repository: svn+ssh://chungyan5.no-ip.org/home/open_data/electronic_computer/modulation_plugin/svn_rep
• Contains circuit PCB and software for dsPic Programmable Clock

Testing Procedure

• For each channel (ch 1 - 4) at pin H2.1, H2.3, H2.5, H2.7
  • Use a CRO to watch the signal
    • Enable the channel
    • Adjust the voltage from 0 - 2.5V (measure accuracy).
    • Adjust the frequency from DC - 200kHz (measure accuracy). If frequency is not accurate, check crystal circuitry.