Difference between revisions of "Minimig Board v1.0 documentation"
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(+ram connections) |
(reorder) |
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| Line 6: | Line 6: | ||
::[[Minimig Board v1.0 MC68000 CPU connections|CPU]] | ::[[Minimig Board v1.0 MC68000 CPU connections|CPU]] | ||
::[[Minimig Board v1.0 RAM connections|RAM]] | ::[[Minimig Board v1.0 RAM connections|RAM]] | ||
| + | ::[[Minimig Board v1.0 Clock generator assignments|Clock generator]] | ||
::[[Minimig Board v1.0 Power assignments|Power]] | ::[[Minimig Board v1.0 Power assignments|Power]] | ||
| − | |||
* [[Minimig Board v1.0 issues|Compiled list of hardware issues]] | * [[Minimig Board v1.0 issues|Compiled list of hardware issues]] | ||
