Minimig FPGA

mongo (070728):
Switching from the Spartan 3 XC3S400 to a Spartan 3E XC3S500E would give you about 17 extra I/O pins while still keeping the 208 pin package. It would also give you a good bit of space for bug fixes and/or future enhancements. The current Minimig design uses up about 82% of the XC3S400, but only 65% of an XC3S500E.

Brand	Chip	LE/LCs	IOs	Package	Price	Distributor
Altera	CycloneII EP2C8Q208I8	8256	138	208-PQFP	$24.30	digikey
Altera	CycloneIII EP3C25Q240C8NES	24624	148	240-PQFP	$39.50	digikey
Xilinx	Spartan3 XC3S400-4PQ208C	8064	141	208-PQFP	$19.25	digikey
Xilinx	Spartan3E XC3S500E-4PQG208C	10476	158	208-PQFP	$20.75	digikey
Xilinx	Enterpoint/Xilinx XC3S1200	?	219	PGA	110 EUR	Enterpoint

Altera chips are slighlty more expensive than Xilinx's.
It is worth considering the Cyclone III if we want to integrate the 680x0 into the FPGA.

However if the cpu is integrated into the fpga, the need for a dedicated board is decreased. One can then use a plain developer board which also include onboard sdram and usually some means of fast communication, Like Digilent XC3S1600E for 295 USD or Enterpoint TF1-250E-1600E for 150 GBP.

FrenchShark:
Use as a south bridge, a CPLD like:

Brand	Chip	Macrocells	IOs	Price	Free Place%Route Linux support
Altera	MAX 3000 EPM3128ATC100-10	128	80	$8.60	No
Xilinx	XL9500XL XC95144XL-10TQ100C	144	81	$5.80	Yes

freqmax: I think that considering Linux support + lower price + consistency with the main fpga. I think that the Xilinx option is better choice.
freqmax: Another consideration is that using an fpga instead of an cpld is that options for larger bus expansions like Zorro bus, Harddisc via ATA etc.. becomes viable. Due capability for faster fpga-fpga communications and more I/Os.

The slow IOs from Paula and the 8520s can be moved to the CPLD.
On a real ECS/OCS Amiga, IOs from the 8520s are updated at 700 kHz, IOs from Paula/Denise are updated at 3.5 MHz.
On a real AGA Amiga, the 8520s are slightly faster : the IOs are updated at 1.4 MHz.
If we run a high speed bus at 28 MHz between the FPGA and the CPLD, each wire can "transport" 8 IOs from paula or 20 IOs from a 8520.
The CPLD basically acts as a giant IO demultiplexer.
Moreover, the CPLDs are 5V tolerant and non-volatile.
There is an application note from Altera describing how to use a MAX as an IO expander :
AN 265: Using MAX II & MAX 3000A Devices as a Microcontroller I/O Expander

Xilinx XC3S400 and XC3S500E comparison
Xilinx XC3S500E
Xilinx XC3S500E pins

schmartboard.com adapter:

The largest Xilinx Spartan-3 FPGA that has less than 400 pins (20x20 matrix) is the FG320 package: http://direct.xilinx.com/bvdocs/publications/ds099.pdf

(FG320 XC3S1500 is also the largest FPGA with Webpack support)

The FG320 package is an 18x18 matrix with 1mm pitch: http://www.xilinx.com/bvdocs/packages/fg320.pdf

Schmartboard 202-0026-01 is BGA 400 Pins, 1.0 mm Pitch: http://www.schmartboard.com/index.asp?page=products_bga&id=110

Diagram of 202-0026-01: http://www.schmartboard.com/schmartboard_pd_202-0026-01.pdf

It would be benefitial if someone can clarify this matter.

Actel FPGA option:

Actel FPGA Unit01 070731

Xilinx Webpack support maximum: XC3S1500 XC3S1600E