Minimig Board v1.0 issues

FYI: Schematics

Schematics: Minimig Board v1.0 schematic

SRAM

Dennis 070725:

• Use a single chip ram like this one, available at digikey for example.

• Replacing the two 512k x 16 with one 1M x 16 bit ram will do away with one chip and free RAM_SEL1

Power

• Include a +5V regulator on board OR use an ATX-style powerplug if you go Mini-ITX. The +5V regulator should be capable of providing about 1A to safely power all peripherals one might attach.

• Peak & average powerconsumption of the minimig v1 ..?

From what I have seen the power consumption is pretty constant. All boards I've built so far consume about 100mA (excluding keyboard/mouse).

• Any power or grounding issues?

I did use a "local-plane" setup. I have set most IO's to slow slewrates and drive currents.

FPGA SPI Dout

• Hardwire the patch needed to get the current board to run. Alternatively, you can also swap pin 81 (IO_L31_4/DOUT/BUSY=SPI_DOUT) and pin 79 (IO_L32P_4/GCLK0=RAM A15) on the FPGA. This way you still have four user-IOs left. You do need to change the .UCF file though and recompile the core.

• PATCH needed to get rev 1 board working:

Disconnect net SPI_DOUT from pin 81 (IO_L31_4/DOUT/BUSY) of FPGA.

Connect net SPI_DOUT to pin 19 (IO_L23N_7) of FPGA (net USER3).

Reason:

Pin 81 is an output during FPGA config that blocks SPI to MMC during startup.

Issue: SD/MMC

• SPI_DOUT from SD-Card via 1k resistor and FPGA (pin81) conflicts ..?

A gate would be better. During normal operation, the SPI out of the MMC card is tristated by disabling the MMC, the same goes at the FPGA side (it's a tristate port). This way, they can share the SPI bus.

• The MMC card interface has a resistor based clock gate circuit around R50,R51. This should be replaced with a proper (single) gate "OR" chip. The margins on this signal are pretty tight on the current board. Also, R49 should be 0 ohm ideally to avoid problems when upgrading the PIC to a newer PIC18LF2620 or something similair. Margins are tight on that signal too atm.
• Footnote: R49 sits between SD/MMC pin7 "D0" and SPI_DOUT (Picture).

Issue: Possible back emf on audio output?

• Headphones may cause back-emf? (maybe supposed to be used as line-out only?)

Issue: X1,X2 operating mode?

• Crystals X1 and X2 is operating in parallel or serial mode ?

Issue: Video D/A inconsistency

• Video D/A have inconsistent resistor values. Use another prefered number series?

Uses 4000, 2000, 1000, 560 ohm per color presently.

Video d/a resistor ladder maths

RS232 pin header wiring

• Connection, RS232:

Internal x86-pc bracket pin mapping

Optimization: Clock generation

• You could consider using a single 20MHz oscillator and figure out how to program the DCM to generator the proper clocks, this would spare a crystal.

Optimization: MCU & FPGA TxD sharing

• MCU(pic18) & FPGA TxD via AND-gate to rid of one jumper:

Yes, no problem. However, all debug output of the PIC has to be disabled as not to interfer with the FPGA serial output.

Optimization: Use cdrom-soundcard cable?

• Connection, Audio:

internal x86-pc cdrom -> soundcard analogue audio pinout

Voltage level: (3.3V/(560ohm + 560ohm + 32ohm))*32 ohm*1000 = 91,7mV

FYI: Power optimisation

Dennis 070803:

• +1.25V and +2.5V can be hooked from +3.3V to save power ?

No gain

• Why is R42 present, it's just sitting between +1,25V and GND?

Provides a minimum load for the LM1117.

FYI: CPU A0

• Why is the CPU pin 19 (A0) not connected to anything ..?

The 68SEC000 is run in 16bit (selected by pin 8 (MODE=Vcc) ) mode, which means that only even addresses are used, hence the lsb address select is not needed.

The addressing of byte wide memory addresses is done using the LDS/UDS strobes.

FYI: SRAM UB/LB

• Why does the SRAM use /UB and /LB when data is 16-bit anyway?

jkonstan 070801:

The UB & LB strobes on the SRAM are due to data bus addressing needed for the 68K cpu. 68K CPU has UDS* strobe for upper byte lane D15-D8 access, and 68K CPU has LDS* strobe for lower byte lane D7-D0 access. When 68K does a read, D15-D0 can be accessed as a word with 68K reading what it requires off of its Databus; however, a write access on a 68K CPU requires the byte lane be qualified. When UDS* active on a write cycle, UB* on SRAM must be active. When LDS* active on a write cycle, LB* on SRAM must be active.

D15........D8	D7........D0
Byte 0= Even	Byte 1= Odd => (Word 0)
/UDS	/LDS
etc..

Ie 68k writes are byte wide.

FYI: SD/MMC pcb layout pins

• The SD-MMC slot has a 12-pin wide connection to pcb.

CD/D3, CMD, GND, VDD, CLOCK, GND, D0, D1, D2, SW#1, SW#2, SW#3

SW#1="gnd", SW#2=open=>write protect, SW#3=open=>no card present

FYI: Fpga pin ordering

• Why is address/data pins to ram/cpu spread around despite dedicated board?

Became such way to ease the PCB layout.

• Why FPGA I/O pins aren't in numerical order?

Was simple when starting out.

FYI: FPGA config voltage

• FPGA configuration mode select M1,M0,M2 (pin 54, 55, 56) pins use VccAUX at +2.5V

FYI: keyboard + mouse wire sharing

• Keyboard and mouse can share connection?

Won't save data lines.

FYI: Port overvoltage protection

• Over/under voltage protection for keyboard or mouse port?

It is a minimal design. The Spartan has built-in ESD protection that this design relies on. :However, monitors and TV's are notorious for blowing up video ports so extra protection has been added there!

FYI: BAV99 is 3-pin

• BAV99 diodes in the schematic is 3-pin not 2-pin as can be thought.

FYI: 15/31kHz missing reference

• 15/31kHz selector is missing reference designation.

FYI: Component sizes

• Component size is missing.

Seems resistor size 0805 or 0603 will fit solder pads. See also Wikipedia: Package sizes

FYI: C37 value

• Value of C37 100uF/6.3V?

Yes

FYI: Video setup

• Video, in 15kHz mode:

/VSYNC = high (scart RGB enable)

/HSYNC = composite sync

FYI: Possible SD/MMC incompability

• Some (esp Sandisk.com) SD/MMC cards aren't standards compliant! see 1541-III FAQ

FYI: Xilinx Place & Route limitation

Xilinx ISE Webpack device support

Free version supports Spartan3 XC3S50 - XC3S1500